The present invention relates to a read only memory (ROM) circuit including metal oxide semiconductor field effect transistors (MOSFET's), and more particularly, to a multi-bit-per-cell ROM circuit in which multi-bit data are stored in each of the MOS transistors making up the ROM circuit.
A memory device of this type is described in "Two-Bits-Per-Cell ROM", M. Stark, Intel Israel Ltd., which was disclosed in "Computer Conference 1981" (p. 209 to p. 212). Each of the MOSFET's used in this ROM, which is constructed as an OR type ROM, is so designed that the ratio W/L of the channel width W to the channel length L changes according to the information to be stored in the MOSFET. However, this OR-type ROM is inferior to an AND-type ROM with respect to its density of integration when fabricated. Nevertheless, the AND-type ROM has never been employed for the multi-bit-per-cell ROM circuit, because if the memory circuit were of the AND-type, it would be difficult to read out the data stored therein.
An AND-type ROM circuit in which one bit is stored in each cell has been known, as shown in FIG. 1. In FIG. 1A, a memory circuit 1 is constructed with a series circuit including memory cells M10 to M13. The memory cells M10 and M12 as enhancement mode n-channel MOS transistors are respectively supplied at the gate electrodes with gate voltages V0 and V2. The memory cells M11 and M13 as the depletion mode n-channel MOS transistors are supplied at the gate electrodes with voltages V1 and V3, respectively. It is assumed that data "0" is stored in the enhancement mode MOS transistors M10 and M12, and data "1" in the depletion mode MOS transistors M11 and M13. An enhancement mode p-channel MOS transistor M14 is connected between a first terminal 2 as a node of the memory circuit 1 and a first power source V.sub.cc. An enhancement mode n-channel MOS transistor M15 is inserted between a second terminal 3 as a node and a second power source V.sub.ss. The node 2 is connected to an input terminal of an inverter 4. The inverter 4 is made up of an n-channel MOS transistor M16 and a p-channel MOS transistor M17 connected in series between the power sources V.sub.ss and V.sub.cc. Data is derived from an output terminal 5 as a connection point between the source-drain paths of the MOS transistor M16 and those of the MOS transistor M17. A clock pulse .phi. is supplied to the gate electrodes of the MOS transistors M14 and M15. In order to read out the data "0" stored in the MOS transistor M12, the gate voltage V2 of the MOS transistor M12 is set to 0 V (an OFF state), and the gate voltages V0, V1 and V3 of the remaining MOS transistors, are set to the first power source V.sub.cc. Then, at time To the clock pulse .phi. is changed from 0 level to V.sub.cc level (FIG. 1B). Upon the level change, the MOS transistor M14 is OFF, the MOS transistor M15 is ON, and the MOS transistor M12 is OFF. Accordingly, the node 2 is kept at V.sub.cc level and the output terminal 5 is kept at "0" level. In other words, the data "0" stored in the MOS transistor M12 is produced from the output terminal 5. For reading out the data "1" of the MOS transistor M11, the gate voltage V1 is set to 0 V and the remaining gate voltages V0, V2 and V3 to V.sub.cc. Then, at time To, the clock pulse .phi. is changed from 0 V to V.sub.cc. The MOS transistors M10 to M13 and M15 are then ON, while the MOS transistor 14 is OFF. Accordingly, the node 2 is at V.sub.ss and the data "1" is derived from the output terminal 5. In this way, the data "1" stored in the MOS transistor M11 is read out. As already stated, the ROM constructed with the logic circuit including the AND type memory circuit 1, as shown in FIG. 1A, has an excellent integration density. In this ROM, it was impossible to store multi-bit data in each of the MOS transistors constituting the ROM, since the ROM is of the current-detection type in which the data is detected depending on the presence or absence of current flow in the memory circuit. Moreover, the ROM using the OR type logic circuit requires contact holes corresponding to each of the MOS transistors forming memory cells, resulting in an increase of the chip area. For these reasons, there has been a great desire for a multi-bit-per-cell ROM circuit which uses an AND-type logic circuit and is capable of storing a plurality of bits in each of the memory cells.